1. Field of the Invention
The invention relates generally to a voltage generator for a flash memory device. More particularly, the invention relates to a voltage generator for a flash memory device capable of implementing a circuit that is not affected by variation in the temperature, power supply voltage and process and freely controlling a low-voltage detection point or a regulation point by controlling the threshold voltages of flash memory cells, in a way that cell currents of over-erased flash memory cells and cell currents of a plurality of weakly-programmed flash memory cells are compared using a plurality of comparators, and a low-voltage detector and a plurality of charge pump circuits are driven depending on the comparison result.
2. Description of the Prior Art
In a flash memory device, in order to program or erase cells, it is required that a given high voltage be applied to each of the terminals of the cells. In order to generate the high voltage being applied to the terminals of the cells, a plurality of charge pump circuits having a pumping circuit and a regulation circuit are required. Also, as it is difficult to correctly perform the program and erase operations at a low voltage, a low-voltage detector for detecting the low voltage is required. Further, in order to operate the low-voltage detector and the plurality of the charge pump circuits, a plurality of comparators for comparing the reference voltage and a given voltage are necessary. A reference voltage generator for generating the reference voltage is also required.
A structure and operation of the conventional voltage generator for a flash memory device having the low-voltage detector, the plurality of the comparators and the plurality of the charge pump circuits will be now described by reference FIG. 1.
If the power supply voltage (Vcc) is divided by first and second resistors R11 and R12, a first comparator 105 compares the divided voltage and the reference voltage (Vref) supplied from the reference voltage generator 101 to produce a low voltage detection signal (LVCC). A first charge pump circuit 102 generates a positive high voltage (VPPD) that will be applied to a first terminal of the cell. A second charge pump circuit 103 generates a positive high voltage (VPPI) that will be applied to a second terminal of the cell. A third charge pump circuit 104 generates a negative high voltage (VEEI) that will be applied to a third terminal of the cell. Each of the first, second and third charge pump circuits 102, 103 and 104 includes a pumping circuit for pumping the high voltage and a regulation circuit for regulating the pumped voltage of the pumping circuit to a desired level. The output voltage (VPPD) of the first charge pump circuit 102 is divided by a first voltage divider 109 having a plurality of PMOS transistors. A second comparator 106 compares a divided voltage (V1) of the first voltage divider 109 and the reference voltage (Vref) and then controls the operation of the first charge pump circuit 102 depending on the comparison result. An output voltage (VPPI) of the second charge pump circuit 103 is divided by the second voltage divider 110 having a plurality of PMOS transistors. A third comparator 107 compares the divided voltage (V2) of the second voltage divider 110 and the reference voltage (Vref) and then controls the operation of the second charge pump circuit 103 depending on the comparison result. Further, the output voltage (VEEI) of the third charge pump circuit 104 is divided by a third voltage divider 111 having a plurality of NMOS transistors. A fourth comparator 108 compares the divided voltage (V3) of the third voltage divider 111 and the reference voltage (Vref) and then controls the operation of the third charge pump circuit 104 depending on the comparison result.
The voltage generator for a flash memory device constructed above is operated by comparing the reference voltage from the reference voltage generator and the respective compared voltage. However, the reference voltage generator is significantly affected by variation in the temperature or process and the power supply voltage. Thus, there is a need for the reference voltage generator that is not affected by those parameters in order to detect or regulate an exact low voltage for the flash memory device. However, there are problems that the reference voltage generator having these characteristics is difficult to implement and the circuit must be modified if there is the difference in the circuit and simulation result.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a voltage generator for a flash memory device that is not affected by variation in temperature, process or the power supply voltage and can exactly detect and regulate a low voltage.
Another object of the present invention is to provide a voltage generator for a flash memory device that is not affected by variation in temperature, process or the power supply voltage and can exactly detect and regulate a low voltage, by controlling cell currents of over-erased flash memory cells and cell currents of weakly-programmed flash memory cells.
Still another object of the present invention is to provide a voltage generator for a flash memory device capable of freely controlling a low-voltage detection point or a regulation point, by adjusting the threshold voltages of the over-erased flash memory cells and the weakly-programmed flash memory cells to control the cell currents.
In order to accomplish the above object, the voltage generator for a flash memory device according to the present invention, is characterized in that it comprises over-erased flash memory cells, at least one or more programmed flash memory cells, and at least one or more comparators for comparing cell currents of the over-erased flash memory cells and cell currents of the programmed flash memory cells, wherein a low voltage is detected and the operations of at least one or more charge pump circuits are controlled, by outputs of the comparators.
In order to accomplish another object, the voltage generator for a flash memory device according to the present invention, is characterized in that it comprises a low-voltage detector for comparing cell currents of different states of two flash memory cells to detect variation in the power supply voltage, and a high voltage generating means for comparing cell the currents of different states of at least two or more flash memory cells to generate at least one or more given high voltages. The high voltage generating means comprises at least one or more charge pump circuits for pumping the power supply voltage to a given high voltage and regulating the pumped voltage to a given level, at least one or more voltage dividers for dividing outputs of the charge pump circuits, respectively; over-erased flash memory cells, at least one or more programmed flash memory cells, and at least one or more comparators for comparing cell currents of the programmed flash memory cells, respectively, based on cell currents of the over-erased flash memory cells and for controlling the charge pump circuits depending on the comparison result.
In order to accomplish still another object, a voltage generator for a flash memory device according to the present invention, is characterized in that it comprises at least one or more load means for supplying the power supply voltage, at least one or more charge pump circuits for pumping the power supply voltages to given high voltages and regulating the pumped voltages to given levels, at least one or more voltage dividers for dividing outputs of the charge pump circuits, over-erased flash memory cells, at least one or more programmed flash memory cells, at least two or more drain bias circuits for adjusting drain voltages of the over-erased flash memory cells and the at least two or more flash memory cells, at least two or more switching means driven by the drain bias circuits to establish current paths of the power supply terminals and the flash memory cells, and at least two or more comparators for comparing each of cell currents of the programmed flash memory cells based on the cell currents of the over-erased flash memory cells to detect decrease in the power supply voltage or to control the charge pump circuits.